Dept. of Electronics Eng. Inst. of Electronics National Chiao Tung University;
Dept. of Electronics Eng. Inst. of Electronics National Chiao Tung University;
Dept. of Electronics Eng. Inst. of Electronics National Chiao Tung University;
Faraday Technology Corp. Hsinchu, Taiwan;
Faraday Technology Corp. Hsinchu, Taiwan;
clock power; multi-bit flip-flops; post-placement optimiza-tion; interval graph; coordinate transformation;
机译:INTEGRA:用于时钟省电的快速多位触发器群集
机译:布线能力受限的多位触发器结构,可降低时钟功耗
机译:用于降低时钟功率的多位触发器的合成
机译:INTEGRA:基于间隔图的快速多位触发器群集,用于节省时钟功率
机译:一种新颖的双边沿触发脉冲时钟TSPC D触发器,适用于高性能和低功耗VLSI设计应用。
机译:基于交叉验证的集群无线传感器网络快速节省资源和抗协作攻击信任计算方案
机译:使用多个电压岛设计的多位触发器时钟网络省电