ISPD 2010 High Performance Clock Network Synthesis Contest: Benchmark Suite and Results

摘要

In the talk, the details of ISPD 2010 high performance clock network synthesis contest will bernintroduced. Compared to first clock network synthesis contest in 2009, the rules have been revisedrnto better reflect the real problems from the industry. Instead of clock latency range upon twornsimulations with different supply voltage settings, the total clock power (modeled by capacitance)rnis set to be the major judging criteria. However, a valid clock distribution network solution mustrnhave local clock skew under a preset limit. Only local clock skew constraints will be enforcedrnbecause (1) early mode timing violations are often limited in local regions, and (2) local timingrnviolations often directly lead to congestion problems which are very hard to fix. Moreover, delayrnvariation will be formulated in the contest and simplified Monte Carlo simulation will be used tornevaluate valid solutions. More importantly, a new set of benchmarks will be announced and used torndecide the winner of the contest. These test-cases are all directly derived from real industrialrnmicroprocessor and high-performance ASIC designs and they have over 1000 clock sinks. Morernthan ten academic clock synthesis tools have participated in the contest and the final results will bernannounced during this talk.