Physical Design Implementation for 3D IC – Methodology and Tools

摘要

3D IC extends interconnect technology across multiple chips,rnmultiple domains (digital, custom/RF, memory) and multiplerntechnology nodes. In addition to the heterogeneous systemrnintegration, 3D IC offers multiple types of configuration such asrn3D IC vertical stack, and silicon interposer. Another dimensionrnof 3D IC is the integration with package, that adds a largernnumber of configuration such as “embedded wafer level packagern= e-WLP” and “3D wafer level package”. All these types of 3DrnIC integration bring together multiple design system (digitalrndesign, custom/analog design, and package design). As such itrnwill require a team of designers with different expertise tornimplement an integrated system of 3D IC.rnThe focus of this invited talk is to explore 3D IC physicalrnmodeling, physical design methodology and physical designrntools. We have added infra-structure in the database, libraryrninterfaces and tools to allow the specification of 3D ICrnconfiguration and interconnect components. Both physicalrndesign tools and analysis tools have been enabled to support 3DrnIC design and analysis using the same modeling and infrastructure.rnWe have developed design methodology with earlyrn3D IC designers that allowed focusing on design flow that isrnoptimized for popular stacking styles.rn3D IC adds new physical components, which must be modeledrnand supported by physical design tools. TSV with backsidernmetal layers and micro-bump (cupper pillars) are examples ofrnthese components. The new components have design rulesrnassociated with them as well as design constraints. The designrnconstraints are added to avoid mechanical stress associated withrnTSV and substrate thinning. Physical design tools such asrnplacement and routing have been enabled to allow the user tornapply these components during the different stages of thernphysical design flow. These enhancements allow the designer tornmaintain the investment in IC tools that are being used andrnapply 3D IC features and design flow in an efficient manner.rnFormal specification is developed to allow the description of 3DrnIC stack configuration and also to describe the types ofrnsignals/power that go through the stack. Both the vertical 3D ICrnstacks and silicon interposer are well supported. In addition tornmanaging the stack, the designer has also the capability to dornearly planning for special signals and power that should traversernthe stack in a shortest distance. High speed signals are examplesrnof those special signals.rnEarly floorplanning is one of the strength of EDI system thatrnallows the designer/design team to plan and implement any 3DrnIC connectivity with new patterns and/or pre-defined patternsrn(TSV and micro-bumps). We have developed several designrnmethodologies to guide the designer during the planning,rnplacement and routing stages. In every design tape-out we haverndone so far, there are usually several signals and power thatrnmust be pre-defined and put in special location on each chip. Wernhave developed automated features allow the placement andrnrouting of TSV and micro-bump in any user defined pattern. Inrnmany cases, the assignment of signals is usually dictated byrnpackage/board design and provides assignment constraints thatrnmust be propagated through the entire stack.rnIn summary, the talk will provide the basic modeling features ofrn3D IC to allow the specification and the integration of multiplernchips in either vertical stack or silicon interposer. Then thernsecond part of the talk is to focus on placement and routing ofrnthe 3D IC interconnect components and how those are integratedrnin a design flow.