Increase the reliability of the gate driver for amorphous TFT displays

摘要

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pulldown structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.