The Parallel Processing Scheme of Digital HDTV Source Decoder

摘要

In this paper, the parallel processing scheme of digital HDTV source decoder based on FPGA is presented. The decoder adopts nine decoding boards for parallel decoding synchronously. This scheme breaks through the speed bottlenck of hardware implementation and improves the system stability. Simultaneously, the problem of motion vectors crossing borders is primely solved by means of adding borderland memories and the decoded sub-pictures can be put together seamlessly.