The Research and Realization on Parallel Distributed VHDL Simulation

摘要

This paper presents a technique for simulating VHDL models on a workstation cluster of general purpose machines via the PVM (Parallel virtual machines) environment. The Simulation and verification are very important steps within the development cycle of an integrated circuit .In particular, the simulation of complex architectures in a hardware description language like VHDL is a major time factor within the design process. To accelerate such a simulation, the distribution of the VHDL model data base and of the simulating data base within a workstation cluster of general purpose machines has been developed. The availability of cheap supercomputing processors and parallel processing software such as PVM have enabled the reutilization of existing software in distributed parallel processing environments. Computations once taking many days with traditional mainframes are now being performed in only a few hours. Compared with other acceleration methods, this distributed simulation method needs no expensive hardware extensions. It uses the temporary idle workstations within a cluster to speed up the simulation. The PVM software provides a unified framework within which parallel programs can be developed in an efficient and straightforward manner using existing hardware. The PVM computing model is simple yet very general and accommodates a wide variety of application program structures. PVM tasks may possess arbitrary control and dependency structures. In other words, at any point in the execution of a concurrent application, any task in existence may start or stop other tasks or add or delete computers from the virtual machine. Any specific control and dependency structure may be implemented under the PVM system by appropriate use of PVM constructs and host language control-flow statement. In this contribution, the basics of VHDL and Distributed discrete-event simulation (DDES) will bediscussed. To get better features and performance, some DDESprotocols assume that simultaneous events may be processed in arbitrary order. We describe a solution of how to apply these algorithms (PVM) to have a correct simulation of the distributed VHDL.