A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference

摘要

Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops during the conversion due to passive charge sharing, causing non-binary DAC switching steps. This is corrected by calculating the charge consumption of critical switching steps and compensating this with a compensation DAC. This scheme with 3b compensation is utilized in a 10b 20MS/s SAR ADC fabricated in 65nm CMOS. With a near-Nyquist input tone, the compensation improves the SNDR by 2.7dB and the SFDR by 11.6dB compared to the uncompensated ADC, achieving 55.4dB SNDR and 68.2dB SFDR. The FoM is 15.7fJ/conv.-step including the reference-voltage driver. Moreover, thanks to the compensation, the decoupling capacitor can be reduced to save chip area.