A 4*2.5 Mchip/s direct sequence spread spectrum receiver withdigital IF and integrated ARM6 core

摘要

This paper reports on a direct sequence spread spectrum (DSSS)nASIC, which integrates all the digital functions of an L-band satellitenpager. The ASIC performs digital IQ-downconversion of a carrier up to 10nMHz running from a 40 MHz clock. The maximum chip rate is 4*2.5 Mchip/s.nThe receiver integrates an ARM6 core, memory, a UART, and flexible DSPnhardware. Therefore, it is fully programmable. The use of macrocells andna self timed architecture allowed the design to have an aggressivendesign time of 7 months from specification to silicon. A low powernredesign of the on-chip downconverter and decimator resulted in 45%npower savings