Automated low-power technique exploiting multiple supply voltagesapplied to a media processor

摘要

This paper describes an automated design technique to reduce powernby making use of two supply voltages. The technique consists ofnstructure synthesis, placement and routing. The structure synthesizernclusters the gates off the critical paths so as to supply the reducednvoltage to save power. The placement and routing tool assigns either thenreduced voltage or the unreduced one to each row so as to minimize thenarea overhead. Combining these techniques together, we applied it to thenrandom logic modules of a media processor chip. The combined techniquenreduced the power by 47% on average with an area overhead of 15% at thenrandom logic, while keeping the performance,