A 4-Gb/s Clock and Data Recovery Circuit Using Four-Phase 1/8-Rate Clock

摘要

This paper describes a 4-Gb/s clock and datarnrecovery circuit exploiting a four-phase 1/8-rate clockrntechnique for low-power and high-speed operation. Thernvoltage-controlled oscillator with an active inductorrnload provides the 50% duty-cycle correction operatingrnat 1/8-rate clock. The four-phase detector performingrn1:4 DEMUX accomplishes a linear frequency and phaserndetection with no systematic phase offset. Test chip wasrnfabricated by a 0.25-μm digital CMOS technology. Thernpeak-to-peak jitter of the recovered clock is 47ps for arnPRBS of length 2~(31)-1. The power dissipation is 70mWrnwith a 2.5-V supply.