A Low Jitter, Low Power, CMOS 1.25-3.125Gbps Transceiver

摘要

This paper describes a high-speed CMOS transceiver that can run at a rate of up to 3.125Gbps, from a 1.8V power supply. The chip includes 10/20:1 full duplex Serializer/Deserializer, (SERDES), novel clock and data recovery circuits, and high-speed differential I/Os. Special techniques have been used to increase the jitter tolerance as well as to reduce the amount of output jitter. The chip has been fabricated in TSMC 0.18u 1P6M digital process and consumes less than 175m W when running at 2.5Gbps with a 26ps deterministic jitter and less than 3.9ps random jitter.