Realization of a real time data flow acquisition and edge detection

摘要

The new technologies that are CMOS sensors and most recent FPGA platform like the Xilinx Virtex-Ⅱ family allow the realization of totally digital active video sensors. On the other hand, the digital visual interface (hereinafter DVI) specification [1] provides a high-speed digital connection for visual data (T.M.D.S). These various technologies led us define a frame grabber - processing - display system based on three components: a CMOS sensor PB-MV13 of Photobit [2], a FPGA platform Virtex-Ⅱ from Xilinx [3] and a T.M.D.S transmitter SiI 160 of Silicon Image [4]. An advantage of this realization is the suppression of the various analogue-digital conversion stages generally used to digitize and restore the video stream. The reconfiguration of the FPGA platform is another advantage, which does not limit processing to a particular purpose and simplify the conception. Besides, an important constraint of this realization is the frame definition 1280x1024 (SXGA) and the rate of 60 images per second with a pixel frequency of 108 MHz.