Sectors: Divide Conquer and Softwarization in the Design and Validation of the Stratix® 10 FPGA

摘要

The Stratix 10 project started with aggressive performance, size, and feature goals, all to be met on a lean schedule. Meeting these performance goals led to a restructuring of the entire configurable clock system into a regular gridded network, which subdivided the device into a composable system of "sectors". Sectors aligned with the needs of the project schedule, since they allowed complexity -- of specification, design, and validation -- to be addressed through "divide and conquer". Similarly, the customary "out-of-band" FPGA management functions including initialization, configuration, test, redundancy, scrubbing, and so on, were reconstituted to run on a collection of per-sector and supervisory processors interconnected by a NoC, whose distributed software would replace centralized tightly coupled finite state machines. This softwarization and parallelization reduced risk, increased flexibility, and increased data bandwidth. During development, parallel teams separately exercised each sector type and its local processor software via the sector's clock and NoC ports, accelerating validation on design databases two orders of magnitude smaller compared to previous methodologies. Even complex features can be added by including new NoC packet types and software rather than painfully adding wires to a rigid floor-plan.