High-Speed RTL Implementations and FPGA Benchmarking of Three Authenticated Ciphers Competing in CAESAR Round Two

摘要

Authenticated ciphers are cryptographic transformations which combine the functionality of confidentiality, integrity, and authentication. This research uses register transfer-level (RTL) design to describe selected authenticated ciphers using a hardware description language (HDL), verifies their proper operation through functional simulation, and implements them on target FPGAs -- the Xilinx Virtex-6 and Virtex-7. The authenticated ciphers chosen for this research are the CAESAR Round Two variants of SCREAM, POET, and Minalpher. To ensure standardization in evaluation, all three candidates are implemented with an identical version of a universal hardware API for authenticated ciphers. Results are compared against each other in terms of performance, area, and throughput-to-area (TP/A) ratio. SCREAM is found to have the highest TP/A ratio of these three ciphers.