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Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure

机译:提高FPGA时序收敛的机器学习方法的分类精度

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We can use Cloud Computing and Machine Learning to help deliver timing closure of FPGA designs using InTime [2], [3]. This approach requires no modification to the input RTL and relies exclusively on manipulating the CAD tool parameters that drive the optimization heuristics. By running multiple combinations of the parameters in parallel, we learn from results and identify which parameters caused an improvement in the final results. By systematically building a classification model and training it with the results of the parallel CAD runs, we can build an accurate estimation flow for helping identify which parameters are more likely to improve the timing. In this paper, we consider strategies for improving the predictive accuracy of our classifier models to help guide the CAD run towards timing convergence. With ensemble learning we are able to increase average AUC score from 0.74 to 0.79, which could also translate into 2.7× savings in machine learning effort.
机译:我们可以使用云计算和机器学习来使用InTime [2],[3]帮助实现FPGA设计的时序收敛。这种方法不需要修改输入的RTL,并且完全依赖于操纵驱动优化启发的CAD工具参数。通过并行运行参数的多个组合,我们可以从结果中学习并确定哪些参数导致了最终结果的改善。通过系统地构建分类模型并使用并行CAD运行结果对其进行训练,我们可以构建准确的估算流程,以帮助确定哪些参数更有可能改善时序。在本文中,我们考虑了用于提高分类器模型的预测准确性的策略,以帮助指导CAD朝着时序收敛发展。通过集成学习,我们能够将AUC的平均得分从0.74提高到0.79,这也可以意味着机器学习工作量节省2.7倍。

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