An Efficient Scheme for Parallelizing Fast Search Algorithm on SIMD Architecture in H.264/AVC

摘要

As the video CODECs become complex increasingly according to the convergence of digital equipments designed for different kinds of specific purposes, the demand of higher performance for video processing is continuously needed. The fast search methods are well known as a representative approach to overcome the performance bottleneck of video encoding. But they require huge computations and dominate most of the running time of video encoding. So, a parallel processing is required to enhance the performance. In general, the fast search methods are difficult to be parallelized because their memory access patterns are not followed by a definite form. This paper proposes a new method for parallelizing a fast search method using linear SIMD architecture with only one-to-one connection between a PE and a memory bank. The simulation results show that the proposed method can reduce nearly 20 percent of running time in the motion estimation (ME).