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Dynamic Control Points and Independent Time Domains for Temporal Logic Falsification

机译:动态控制点和独立时域,用于时间逻辑伪造

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摘要

Temporal logic falsification is an approach to model-based testing, where test cases are generated from a temporal logic specification and are run on a system-under-test to determine whether the system-under-test falsifies the temporal logic specification. In this paper, we report on two extensions on an existing temporal logic falsification approach, implemented in the S-Taliro tool. The two extensions concerns dynamically determining the number of control points in the process of search for test-cases and also, decoupling the different time domains in the n-dimensional input search space. We have conducted an experimental analysis of our approach on two benchmarks: an automatic transmission system (from the automotive domain) and a delta-sigma modulator (from the electrical domain). The results indicate a significant improvement over the existing approach. The full paper concerning this research is accepted for publication in the proceedings of A-MOST 2018.
机译:时间逻辑伪造是一种基于模型的测试方法,其中,测试用例是从时间逻辑规范生成的,并在被测系统上运行以确定被测系统是否伪造了时间逻辑规范。在本文中,我们报告了在S-Taliro工具中实现的现有时态逻辑伪造方法的两个扩展。这两个扩展涉及在确定测试用例的过程中动态确定控制点的数量,以及将n维输入搜索空间中的不同时域解耦。我们已经对我们的方法进行了两个基准的实验分析:自动变速箱系统(来自汽车领域)和delta-sigma调制器(来自电气领域)。结果表明,与现有方法相比有了显着改进。有关该研究的全文在A-MOST 2018会议录中被接受发表。

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