An energy-aware set-level refreshing mechanism for eDRAM last-level caches

摘要

Since embedded DRAM (eDRAM) has a higher density with a lower leakage power than SRAM, it is promising to be used as the last-level cache (LLC) of a microprocessor. However, an eDRAM LLC needs a high energy consumption for refresh operations. In particular, the conventional eDRAM LLC refreshes even dead cache lines that are not reused until their evictions. This paper proposes an energy-aware set-level refreshing mechanism to reduce the wasted energy due to unnecessary refreshes of dead cache lines. In the case where the cache resources are excessive compared with the demand of an application, the excessive resources are wasted to store dead lines. Therefore, the proposed mechanism dynamically adjusts the number of refreshed cache lines. The evaluation results show that the proposed mechanism can reduce the LLC energy consumption by 46% with a 1% performance loss on average.