Design Exploration of Small Bit-Width Multipliers Using Approximate Logic Design (ALD) Tool

摘要

Power consumption is one of the most pressing features to consider when developing embedded platforms. Approximate or Inexact computing has been proposed as a possible solution to address power consumption by utilizing the error resilience of some applications. This requires the design process to trade-0ff accuracy and power consumption. In this paper, the design exploration for a 4×4 unsigned approximate multiplier is pursued using a novel Approximate Logic Design (ALD) tool. The results are used to assess the 4×4 Approximate Multiplier Design (AMD) with the best performance as basic building block for larger designs. The 4×4 AMD is then used to design a 8×8 AMD unsigned multiplier. Metrics for these AMD multipliers are established at 45nm CMOS technology using Synopsys Design Compiler. Error Metrics are also calculated, the results are compared with existing unsigned approximate multipliers found in the technical literature. These results show that the proposed designs perform very well when both the Power-Delay Product (PDP) and the Normalized Mean Error Distance (NMED) are considered. To prove the validity of the proposed designs, an image filtering application is employed; an improvement in Peak Signal-Noise-Ratio (PSNR) is achieved compared with existing designs.