Analysis of Static Analog Linearizer Architectures for Power Amplifiers

摘要

As next generation (5G) cellular transmitters are foreseen to operate with very wide bandwidths, and with aggregates of medium-power amplifiers, the traditional use of digital predistortion (DPD) will be certainly restricted. Therefore, the incorporation of analog circuitry along with the power amplifier to compensate, in part, the generated distortion is a plausible solution to relax the complexity of the DPD algorithms. In this sense, this paper presents an analysis of possible architectures for implementing static analog linearizers for power amplifier circuits, indicating their advantages and disadvantages. The objective is to provide system level support for possible implementations of analog linearizers.