National Engineering School of Tunis (ENIT), Communications Systems Laboratory (SysCom), University of Tunis El Manar (UTM), Tunisia;
National Engineering School of Tunis (ENIT), Communications Systems Laboratory (SysCom), University of Tunis El Manar (UTM), Tunisia;
National Engineering School of Tunis (ENIT), Communications Systems Laboratory (SysCom), University of Tunis El Manar (UTM), Tunisia;
National School of Engineering of Bizerte (ENIB), Communications Systems Laboratory (SysCom), University of Carthage, Tunisia;
digital signal processing chips; multiprocessing systems; scheduling;
机译:BWT和LZ77无损数据压缩算法的并行硬件/软件体系结构
机译:基于抢占式硬件调度程序引擎和不同调度算法的nMPRA CPU体系结构的实现
机译:并行机器提前/拖后调度问题中的最优公共到期日分配和最优调度策略的遗传算法
机译:数据并行硬件架构的最佳调度算法
机译:智能非易失性存储器控制器的设计:体系结构建模,系统分析,并行I / O处理和调度算法。
机译:具有加权后期工作准则和共同到期日的并行同机调度问题的元启发式算法
机译:遗传算法硬件架构在最优数据包调度中的应用