A 1.25–12.5Gb/s 5.28mW/Gb/s multi-standard serial-link transceiver with 32dB of equalization in 40nm CMOS

摘要

This paper describes the design of a serial-link transceiver that supports various communication standards from 1.25 to 12.5Gb/s, implemented in 40nm CMOS technology. Both DC and AC coupling mode can be provided by the receiver, in which a wide range PI-based CDR is also proposed. The transceiver utilizes a 3-tap FFE, a 2-stage CTLE and an adaptive 2-tap DFE to achieve the compensation for a Nyquist channel loss of 32.4dB, and consumes 66mW from a 1.1V supply when operating at 12.5Gb/s.