Subthreshold adiabatic logic (SAL) based building blocks for combinational system design

摘要

Sub-threshold Adiabatic Logic (SAL), is a power saving technique that could be used for applications which demands very low power consumption and are not performance intensive. In this paper SAL is studied and the basic building blocks for combinational systems are implemented and simulated using Cadence in 45nm technology node. Results are compared with corresponding CMOS implementations considering power delivered from source, delay in signal propagation and computed Power Delay Product (PDP). It is observed that relative power delivered from the source is reduced by almost 50dB in case of SAL compared with respective CMOS implementation.