Department of Electrical, Engineering, Shahid Beheshti University, Tehran, Iran;
Department of Electrical Engineering, Mathematics and Computer Science, University of Twente Enschede, Netherlands;
Department of Electrical Engineering Shahid Beheshti University Tehran, Iran;
Electrical engineering; Handheld computers; Computer architecture; Digital systems; Mathematics; Computer science; Indexes;
机译:基于EMD的图像隐写术的新型高速可重构FPGA体系结构
机译:基于EMD的图像隐写术的新型高速可重新配置FPGA架构
机译:采用开关电容正反馈比较器和并行单门编码器的高速低功耗闪存ADC架构
机译:基于高速低功耗上下文的隐写术的新型算法与架构
机译:用于错误控制编码和自适应视频缩放的低功耗,高速算法和VLSI架构。
机译:植入式神经解码器的仿生自适应算法和低功耗架构
机译:新的高速和低功耗radix-2r乘法算法。
机译:基于算法的低功耗变换编码体系结构。第2部分。对数复杂性,统一架构和有限精度分析。