Exclusive control for compound operations on hardware transactional memory

摘要

Transactional memory (TM) is a lock-free synchronization mechanism for shared memory systems, and it is a promising paradigm for complementing or replacing conventional lock-based techniques. On TM, read-after-read (RaR) accesses cause no conflict and do not prevent parallel speculative execution of transactions. However, quite a few of read accesses are followed by write accesses to the same variables or addresses, for example in compound operations such as increment or decrement. We found that granting such RaR access requests causes futile stalls which impact TM performance seriously. In this paper, we propose a novel effective transaction scheduling for hardware transactional memories by controlling such RaR accesses with very small additional hardware costs. If an RaR access to an address is expected to be followed by a write access to the same address, the transactions concerned with the access are serialized. The result of the experiment shows that the execution time of HTM is reduced 72.2% at a maximum and 17.5% on average with our transaction scheduling.