Natural logarithm and division floating-point high throughput co-processor implemented in FPGA

摘要

New floating-point co-processor computing natural logarithm, division and MACs is presented. The co-processor hardware architecture is optimized to high throughput 32-bit floating-point single precision computations. The co-processor is technology independent. It is implemented in FPGA. The co-processor generates new natural logarithm result in every 6 clock cycles and new division result in every 5 clock cycles. The proposed co-processor is oriented and designed for high computational demanding signal processing applications.