Current-steering DAC linearisation by impedance transformation

摘要

This paper proposes the design of a load-network for the current-steering DAC which highly enhances its performance. Foremost, the effect of the load-network on the DAC's performance is analysed. Based on this analysis design specifications for a linear 12+1 bit DAC are derived. The presented circuit implementation is a 4th order lowpass realizing broadband impedance transformation in the 65 nm TSMC process. This design makes an operation from 4 to 6 GHz possible. The proposed load-network enhances the error-vector-magnitude by 4.8 dB in contrast to a 50 Ω-load.