Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
School of Computer Science, University of Lincoln, Lincoln, LN6 7TS, UK;
School of Computer Science, University of Lincoln, Lincoln, LN6 7TS, UK;
Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
Institute of Microelectronics, Tsinghua University, Beijing, 10084, China;
Jitter; Clocks; Bandwidth; Transfer functions; Solid state circuits; Conferences; Oscillators;
机译:基于改进的二阶数字滤波器,滞回选集和阶段内插器的CDR系统
机译:基于改进的二阶数字滤波器,磁滞投票器和相位插值器的CDR系统
机译:基于改进的二阶数字滤波器,磁滞投票器和相位插值器的CDR系统
机译:具有抖动抑制滤波器和相位补偿内插器的改进的40 Gb / s CDR
机译:具有LC延迟线VCO的10 Gb / s CDR / DEMUX,位于0.18微米CMOS中。
机译:使用插值三次样条的钨阳极光谱模型:20 kV至640 kV的未过滤X射线光谱
机译:8.7基于65nm CMOS的1至6Gb / s相位内插器的突发模式CDR