The proposed Clock and data recovery system（CDRS） has three improved parts. The second order digital filter with rounding algorithm implements fractional gain and avoids direct current quantization noise which varies between –q/2 and +q/2 while that of traditional filter varies between 0 and +q（q is quantization step）. The hysteresis majority voter can combat high frequency and strong jitter especially in quasi-steady state. The improved Phase interpolator（PI） has much smaller current-switching glitch and phase glitch since the weighting current changes gradually instead of steeply.The optimized CDRS can handle up to ±6000 ppm（parts per million） frequency offset and the phase resolution is ■/LSB（Least significant bit） according to analysis. The simulations of jitter transfer function and jitter tolerance by Matlab, simulations of phase noise by spectre using Verilog+Verilo A model, and measurements of frequency offset and jitter tolerance all show its good performance.
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