首页> 外文会议>2015 IEEE International Conference on Innovations in Information , Embedded and Communication Systems >Performance enhancement of the junctionless surrounding gate transistor with high Ion/Ioff ratio
【24h】

Performance enhancement of the junctionless surrounding gate transistor with high Ion/Ioff ratio

机译:高I ​​ on / I off 比的无结环绕栅晶体管的性能增强

获取原文
获取原文并翻译 | 示例

摘要

This paper presents a brief description of a uniformly doped junctionless surrounding gate MOSFET. The proposed device is a thin nanowire has equal doping concentration throughout source, channel and drain region. This device provides very low leakage current, high on current and high on-off current ratio. The absence of the ultra shallow junctions in the conventional MOSFETs makes this device easy to fabricate, by eliminating costly annealing and etching techniques. The simulation result stipulates that junctionless transistor is a promising device for the future electronics.
机译:本文简要介绍了均匀掺杂的无结环绕栅极MOSFET。所提出的器件是一条细纳米线,在整个源,沟道和漏区具有相同的掺杂浓度。该器件提供极低的泄漏电流,高导通电流和高导通/截止电流比。通过消除昂贵的退火和刻蚀技术,常规MOSFET中不存在超浅结,因此该器件易于制造。仿真结果表明,无结晶体管是未来电子产品的有希望的器件。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号