Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan;
field programmable gate arrays; logic design; storage management; FPGA memory hierarchy; OpenCL memory model; application types; application-specific memory hierarchy design; application-specific memory optimizations; design compilation; design synthesis; high-level synthesized OpenCL kernel codes; memory management; Bandwidth; Field programmable gate arrays; Hardware; Kernel; Memory management; Optimization; Random access memory; Data Reuse; FPGA; High-level Synthesis; Memory Hierarchy; OpenCL;
机译:FPGA上的OpenCL内核的优化实现
机译:针对FPGA合成的OpenCL设计的低密度奇偶校验解码器性能的优化
机译:FPGA上针对OpenCL应用程序的基于LLVM的内存去耦自动化
机译:用于高级合成OpenCL内核的FPGA存储层次结构
机译:在靶向FPGA的高级合成中长短期记忆神经网络的实施
机译:EDSSA:基于OpenCL的FPGA平台上的编码器 - 解码器语义分段网络加速器
机译:传递指针:探索FPGA的OpenCL工具中的共享虚拟内存抽象