Based IBIST auto-parallel reconfiguration of TSV defect in 3D-IC

摘要

TSV or interconnect between chips have as a promising solution for overcoming interconnect and power bottlenecks in 3D IC. However, testing of 3D ICs remains a significant challenge, and breakthroughs in test technology are needed to make 3D integration commercially viable. This paper first presents an overview of TSV-related defects and the impact of TSVs in the form of new defects in devices and interconnects. Then, we propose an improvement of IBIST by a circuit reconfiguration to help us to use the same circuit in the presence of default interconnections. This paper first presented an overview of TSV defects. Then, we propose an improvement of IBIST (Interconnect Build-In Self-Test) by a circuit reconfiguration RIBIST in order to overcome the obstacles.