Dept. of ETC Eng., DYPCOE, Pune, India;
field programmable gate arrays; floating point arithmetic; hardware description languages; FPGA; HDL; IEEE double precision floating point numbers; Verilog hardware description language; Xilinx ISE14.1i; addition-subtraction module; complex systems; floating point arithmetic; Computer architecture; Digital signal processing; Field programmable gate arrays; Hardware design languages; Lead; Standards; Adder/Subtractor; Double precision; FPGA; Floating Point; IEEE754; Verilog;
机译:Fpga上的快速浮点双精度实现
机译:在FPGA上用于浮点双精度及更高乘法器
机译:FPGA多精密浮点算术单元的设计与实现
机译:使用Verilog的双重精度浮点数的加法/减法模块的FPGA实现
机译:含咖啡因的FPGA:用于训练和推理卷积神经网络的FPGA框架,具有降低的精度浮点算法
机译:基于Horprasert模型的实时背景扣除的FPGA实现
机译:使用Verilog的双精度浮点加法器和减法器的实现