An open source Verilog front-end for digital design analysis at word level

摘要

We develop an open source Verilog front-end that compiles a digital circuit design into the circuit description at high level. Such description is a component net-list at a higher level than the gate net-list. In the component net-list, all high level information such as bit vector data-paths, finite state machines and counters are retained. Thus, the proposed front-end is suitable for newly proposed back-end algorithms that use high level information to synthesize, optimize and verify the circuit. Our front-end is able to parse large open-source designs.