Optimized implementation of Discrete Wavelet Transform with area efficiency

摘要

The objective of this paper is to illustrate a comparative study on the performance of DWT with the multiplier reducing algorithms. The optimization techniques were based on the identification of algorithms, which could exploit the FPGA features. Discrete Wavelet Transform (DWT) is one of the most used techniques for image compression and is applied in a large category of applications for multi resolution analysis of signals. DWT can provide significant compression ratios without great loss of visual quality than the previous techniques such as the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT). This work provides an analysis between the conventional VLSI implementation techniques as against an area efficient realization approach. This is expected to provide a reduction in hardware complexity and also an increase in computational speed. The reduction in the resource utilization improves the system performance by means of reduction in power consumption as well as the reduction in delay.