Parallel implementations of the discrete wavelet transform and hyperspectral data compression on reconfigurable platforms: Approach, methodology and practical considerations.

摘要

This work was motivated by the need to dramatically reduce communication data rates for space based hyperspectral imagers. Key issues are compression effectiveness, suitability for scientific processing of retrieved data, and efficiency in terms of throughput, power and mass. We address the problem in three stages: first, development of a Field Programmable Gate Array (FPGA) hardware implementation of the parallel Discrete Wavelet Transform (DWT); second, development of a hyperspectral compression algorithm based on the wavelet transform and suitable for spacecraft on-board implementation; and third, development of an FPGA-based hyperspectral data compression "system on a chip" (SoC).;In developing our hardware-implemented parallel DWT, our contributions are: a structured methodology for moving the 2D DWT, and similar algorithms, into reconfigurable hardware such as an FPGA; a specific representation for the DWT that provides an architecture suitable for efficient hardware implementation; and a data transfer method that provides seamless handling of boundary and transitional states associated with parallel implementations. The resultant new implementation produced significantly improved performance over previous methods.;In developing our hyperspectral data compression algorithm, our contributions are: a DWT based algorithm, capable of both lossy and lossless compression, that can be tailored to accommodate any scientific instrument, and that is suitable for on-board hardware implementation; algorithm components that are efficiently designed for three dimensional data, for implementation in hardware, and that achieve results comparable to or exceeding previous optimized algorithms at a lower computational cost; the discovery of, and development of mitigation techniques for, a new artifact-producing phenomenon encountered when using the 3D DWT for compression; and a new technique for region-of-interest compression of hyperspectral data that uses "virtual scaling", satisfies low memory requirements, and provides better compression effectiveness.;In developing our FPGA-based SoC, our contributions are: development of a scalable embedded implementation for the 3D DWT hyperspectral data compression; a novel priority-based data formatting and localization technique for bit-plane encoding that provides substantial improvements in throughput efficiency compared to standard techniques; and extension of the wavelet transform methodology developed in the first part to hybrid Hardware/Software SoC implementations.