A multi-band fully differential fractional-N PLL for wideband reconfigurable wireless communication

摘要

A fractional-N PLL for multi-standard transceiver is presented. The tuning range covers dual bands of 0.38∼6GHz and 9~12GHz. A high-speed ultra-band divide-by-2 circuit is designed to accomplish the frequency band of 0.3 to 13.7GHz. A novel high isolation multiplexer is presented to achieve the frequency band selection in LO paths. This chip was implemented with 65nm CMOS technology and the maximum current consumption is 20.05mA at 1.2V power supply. The measured typical phase noise of the PLL is −114.6dBc/Hz from 1MHz offset for 4.85GHz output and the reference spur and fractional spur are less than −48dBc and −62.99dBc respectively.