This paper presents a novel test generation technique for defective power TSV induced path delay faults in 3D IC. This paper provides a simple close-form analysis to show that, in a regular 3D power grid model, open defects in power TSV do not induce serious IR drop. However, leakage defects in power TSV should be tested, even though the number of power TSV is large. This paper proposes a test generation flow to detect path delay faults induced by defective power TSV. The proposed technique is demonstrated on an 18-tier, 7 x 7 multi-core 3D IC model. In the experiment of b18 and b19 benchmark circuits, all detectable path delay faults induced by power TSV can be tested by around hundred test patterns. This technique requires no extra DfT hardware overhead.
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机译：本文提出了一种新颖的测试生成技术，用于3D IC中功率缺陷TSV引起的路径延迟故障。本文提供了一种简单的封闭形式分析，以表明在常规3D电网模型中，功率TSV中的开放缺陷不会引起严重的IR下降。但是，即使电源TSV的数量很大，也应测试电源TSV中的泄漏缺陷。本文提出了一种测试生成流程，以检测由功率缺陷TSV引起的路径延迟故障。在18层7 x 7多核3D IC模型上演示了所提出的技术。在b18和b19基准电路的实验中，由功率TSV引起的所有可检测到的路径延迟故障都可以通过大约一百种测试模式进行测试。此技术不需要额外的DfT硬件开销。
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