Application of timing variation modeling to speedpath diagnosis

摘要

The impact of timing variations on the performance of Very-Large-Scale Integrated (VLSI) circuits is increasing as the feature sizes shrink down into the nanometer scale. Timing variations induced by process, environmental or other effects may lead to a failing speedpath. In this paper, first a functional model of circuit timing is constituted. Then, timing variations are added to the model. Afterwards, this model is utilized to diagnose failing speedpaths.