Opamp-sharing MDAC design for pipelined successive-stage of a 1.8V 80MS/s 14-bit pipelined ADC

摘要

A design of opamp-sharing multiplying digital-to-analog converter (MDAC) used in the successive stages of an 80MS/s 14-bit pipelined analog-to-digital converter (ADC) with 1.8V supply voltage is presented in this paper. Opamp-sharing structure of the paper is proposed to achieve low-power operation, and SC-CMFB (switch capacitor-common mode feedback) circuit further reduces power consumption. The gain-boost structure of the amplifier is used to meet the precision requirement of the MDAC. The memory effect is completely eliminated with clock-resetting phase. The circuit design is implemented in the Chartered 0.18um CMOS process and the simulation results show that the designed MDAC could meet performance requirements of the pipelined ADC, consuming 10.5mW power.