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Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

机译:低复杂度编码器的简化多级准循环LDPC码

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In this paper we propose a parity check matrix construction technique that simplifies the hardware encoders for Multi-Level-Quasi-Cyclic (ML-QC) LDPC codes. The proposed construction method is based on semi-random - ML-QC extension and appropriately selects shifting factors to reduce the density of the inverted matrix used in several encoding algorithms. The construction method derives low-complexity encoders with minimal degradation of error-correction performance, observable at low BER only. Furthermore a VLSI encoding architecture based on the suggested parity-check matrix (PCM) is also introduced. Experimental results show that the complexity of the proposed encoders depends on the density of the binary base matrix. A comparison with random QC codes reveals substantial complexity reduction without performance degradation for cases of practical interest. In fact a hardware complexity reduction by a factor of 7.5 is achieved, combined with the acceleration of the encoder, for certain cases.
机译:在本文中,我们提出了一种奇偶校验矩阵构造技术,该技术简化了多级准循环(ML-QC)LDPC码的硬件编码器。所提出的构造方法基于半随机-ML-QC扩展,并适当选择移位因子以降低几种编码算法中使用的倒置矩阵的密度。这种构造方法可以得到低复杂度的编码器,并且纠错性能的下降最小,仅在低BER时才能观察到。此外,还介绍了基于建议的奇偶校验矩阵(PCM)的VLSI编码架构。实验结果表明,所提出的编码器的复杂度取决于二进制基矩阵的密度。与随机QC码的比较表明,在实际应用中,可以显着降低复杂度,而不会降低性能。实际上,在某些情况下,结合编码器的加速度,可以将硬件复杂度降低7.5倍。

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