A new multilevel inverter topology with reduced number of power switches

摘要

Recent years have seen the emergence of various multilevel inverter topologies for high voltage and high power applications. This is mainly due to the attractive advantages of multilevel inverters such as lower Total Harmonic Distortion (THD) in the output voltage, higher efficiency, less stress on the power switches and low Electromagnetic Interference (EMI). The main problem of using multilevel inverters is the number of power switches that normally contributes to the complexity in controlling the power switches and high cost. In this paper a new structure of a nine-level inverter is proposed to improve the multilevel inverter performance by compensating these disadvantages. This topology employs fewer power switches compared to that of conventional multilevel inverters. In addition a modified Pulse width Modulation (PWM) control method has been designed for this new inverter structure that requires less number of carrier signals. The proposed topology and its control method are described and the results of a simulation study conducted have illustrated the performance of the overall system, thus revealing the advantages of this structure compared to conventional topologies.