In order to optimize logic libraries for high-speed operation, and be able to compare new library designs with existing ones, a method that allows switching frequency measurement on-chip is required. In this paper we present a measurement technique to evaluate the switching frequency (and therefore the maximum speed) of digital circuits. The method utilizes asynchronous logic, and is flexible - allowing measurements and comparison to be performed on digital circuits of varying complexity. This measurement method was integrated onto an IC in a 65nm CMOS technology. We provide simulation results that show that the technique is not only able to provide switching frequency measurements but can also identify the critical path through the circuit under test. Such information is critical for logic library optimization.
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