首页> 外文会议>2012 IEEE 55th International Midwest Symposium on Circuits and Systems >A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss
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A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss

机译:新颖的4到3降压片上SC DC-DC转换器,降低了底板损耗

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This paper presents a novel fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports programmable regulated load voltage ranging from 2.6V to 3.2V out of 5V input supply. MOS capacitors are used for flying capacitors (600pF) and load capacitor (400pF) in this implementation. To minimize the bottom-plate parasitic capacitor related loss while maximizing the load current driving capability, the proposed 4-to-3 step-down topology utilizes two differently sized conventional 2-to-1 step-down topologies, each of which has different value of flying capacitor. In addition, the proposed implementation reduces switching loss and control circuit loss since the internally generated output voltage of the bottom 2-to-1 block is used as the supply for the control circuits throughout the small internal LDO regulator. The proposed converter is designed and simulated using high-voltage 0.35µm BCDMOS technology. The programmable output voltage is regulated by means of pulse frequency modulation (PFM) technique using 18-bit shift register and digitally controlled oscillator (DCO). The proposed switched-capacitor converter achieves the peak efficiency of 72% while it delivers the load current between 1mA and 10mA. 10-phase interleaving technique enables the output voltage ripple of the load voltage to be less than 1%.
机译:本文介绍了一种新型的全集成片上开关电容器(SC)DC-DC转换器,该转换器在5V输入电源中支持2.6V至3.2V的可编程稳压负载电压。在此实现中,MOS电容器用于飞跨电容器(600pF)和负载电容器(400pF)。为了最大程度地减小与底板寄生电容相关的损耗,同时最大程度地提高负载电流驱动能力,建议的4至3降压拓扑结构利用两种不同尺寸的常规2对1降压拓扑结构,每种拓扑结构的值都不同。飞电容器。另外,由于底部2对1块的内部生成的输出电压被用作整个小型内部LDO稳压器的控制电路电源,因此,所提出的实现方式还降低了开关损耗和控制电路损耗。拟议的转换器使用0.35µm高压BCDMOS技术进行设计和仿真。可编程输出电压通过使用18位移位寄存器和数控振荡器(DCO)的脉冲频率调制(PFM)技术进行调节。所提出的开关电容器转换器在提供1mA至10mA的负载电流时,可实现72%的峰值效率。 10相交错技术使负载电压的输出电压纹波小于1%。

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