Synchronizers play a key role in multi-clock domain systems on chip. One of the essential points in designing reliable synchronizers is to estimate and evaluate synchronizer parameters and Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This paper shows that those rules of thumb and some common simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose a new simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state of the art simulation methods. Simulation results for each of the analyzed methods are compared with measurements of a 65nm LP CMOS test-chip.
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