FPGA implementation of a fast pipeline architecture for JND computation

摘要

Just Noticeable Distortion (JND) based on human visual system (HVS) is widely used in the transparent watermarking. But the computation of JND is very complex, which makes it difficult to embed it into integrated circuits. To solve this problem, Haar Wavelet based JND model is exploited in this paper. Furthermore, the fast pipeline architecture based on haar-wavelet for JND computation is developed. The architecture is modeled with hardware description language, and implemented on Altera EP2C35 FPGA device in order to evaluate the its performance. The hardware cost of JND core is 1460 Logic Cell combinations and 330 registers, which is significantly smaller than the Full Band JND based architecture. From the experiment results, the system goes on well with a 120MHz clock. Compared with the full band JND based architecture, ours achieves 75% time saving.