Low power analog to digital convertor with digital calibration for sensor network

摘要

A low-power analog-front-end (AFE) LSI for sensor networks—based on an analog-to-digital convertor (ADC) with digital calibration—was developed. Power consumption of the ADC in the AFE LSI was reduced by applying digital calibration. As a result, the proposed successive approximation register (SAR) ADC achieves both high effective resolution (11.7 bits) and extremely low power consumption (2.5 mW) at 1 Msps. Moreover, average power consumption of the AFE LSI (including the ADC) is about 5 µW, which is low enough for sensor networks.