Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS

摘要

This paper presents circuit techniques to improve read capability for single-end SA ROM design fabricated in UMC 55nm process. DV0 and DV1 margin are key features reflect read capability, and result show that DV0 enhanced significantly by using WL boosting schemes and DV1 enhanced by SA PMOS compensation (SAPC) structure. Combining WL boosting and SAPC technologies, the read fail problem in ROM could be solved easily which bring by leakages especially under 60nm process.