FPGA based cascaded multilevel pulse width modulation for single phase inverter

摘要

This article explores the development of FPGA based controller for conventional and cascaded multilevel PWM single phase inverter. The conventional multilevel inverter is constructed by the H-bridge and cascaded multilevel inverter constructed by two full H-bridges. FPGA logic device is chosen for the hardware implementation of control circuit. VHDL language is used to model the inverter switching strategies. The proposed controller generates 4 and 8 control signals for conventional multilevel inverter and cascaded multilevel inverter respectively. These inverters provide 3-level and 7- level output voltages. Matlab/System generator and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. These inverter topologies with filters would have reduced harmonics and can operate at high efficiency.