首页> 外文会议>2009 International conference on semiconductor technology for ultra large scale integrated circuits and thin film transistors (ULSIC vs. TFT) >Three-dimensional Finite Element Analysis of Phase Change Memory Cell with Thin TiO_2 Stop Layer used for Forming Deep Sub-micro Electrode
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Three-dimensional Finite Element Analysis of Phase Change Memory Cell with Thin TiO_2 Stop Layer used for Forming Deep Sub-micro Electrode

机译:具有薄TiO_2停止层的相变存储单元用于形成深亚微电极的三维有限元分析

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摘要

Thin TiO_2 layer inserted in phase change memory (PCM) cell to form Deep sub-micro Bottom Electrode (DBE) was interposed and its electrical-thermal characteristics were investigated with finite element analysis. Compare with other dielectric material, TiO_2 with good heat stability and low heat conductivity is suitable for preventing heat diffusion from phase change region. Besides, TiO_2 layer as stop layer during Chemical Mechanical Planarization (CMP) can effectively control the height of deep sub-micro electrode. Additionally, there exits the appropriate height of DBE (200nm) to contribute more heat during RESET operation. Compared with the conventional cell (SiN layer), the RESET threshold current of the DBE cell is reduced from 1.8mA to 1.2mA. It is illustrated in simulation results that the ratio of amorphous resistance and crystalline resistance will be larger in RESET operation when TiO_2 film is 10nm approximately. Therefore, not only TiO_2 film is stop layer during sub-micro electrode fabrication, but also is it benefiting for writing current reduction.
机译:插入相变存储(PCM)单元中的TiO_2薄层以形成深亚微底部电极(DBE),并通过有限元分析研究其电热特性。与其他介电材料相比,具有良好的热稳定性和低导热性的TiO_2适合防止热从相变区扩散。此外,TiO_2层作为化学机械平坦化(CMP)过程中的终止层可以有效地控制深亚微电极的高度。此外,存在适当的DBE高度(200nm),以便在RESET操作期间产生更多的热量。与传统单元(SiN层)相比,DBE单元的RESET阈值电流从1.8mA降低至1.2mA。仿真结果表明,当TiO_2薄膜约为10nm时,在RESET操作中,非晶电阻和结晶电阻之比会更大。因此,在亚微电极制造过程中,不仅TiO_2薄膜是阻挡层,而且有利于降低写电流。

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  • 会议地点 Xian(CN);Xian(CN)
  • 作者单位

    State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. Shanghai 200050, China,Graduate School of the Chinese Academy of Sciences, Beijing 100049, China;

    State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. Shanghai 200050, China;

    State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. Shanghai 200050, China;

    State Key Laboratory of Functional Materials for Informatics, Laboratory of Nanotechnology, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences. Shanghai 200050, China;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 大规模集成电路、超大规模集成电路 ;
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